ARM system-on-chip architecture /

Détails bibliographiques
Auteur principal: Furber, Stephen B. (Stephen Bo), 1953-
Format: Livre
Langue:Inglés
Publié: New York : Addison-Wesley, c2000.
Édition:2nd. ed.
Sujets:
Microprocesador.
Procesamiento de datos.
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100 1 |a Furber, Stephen B.  |q (Stephen Bo),  |d 1953-  |9 84550 
245 1 0 |a ARM system-on-chip architecture /  |c Steve Furber. 
250 |a 2nd. ed. 
260 |a New York :  |b Addison-Wesley,  |c c2000. 
300 |a xii, 419 p. :  |b il. ;  |c 23 cm. 
504 |a Incluye referencias bibliográficas (p. 410-411) e índice. 
505 0 0 |g 1.  |t Introduction to Processor Design --   |t Processor architecture and organization --   |t Abstraction in hardware design --   |t MU0 - a simple processor --   |t Instruction set design --   |t Processor design trade-offs --   |t Reduced Instruction Set Computer --   |t Design for low power consumption --   |g 2.  |t ARM Architecture --   |t Acorn RISC Machine --   |t Architectural inheritance --   |t ARM programmer's model --   |t ARM development tools --   |g 3.  |t ARM Assembly Language Programming --   |t Data processing instructions --   |t Data transfer instructions --   |t Control flow instructions --   |t Writing simple assembly language programs --   |g 4.  |t ARM Organization and Implementation --   |t 3-stage pipeline ARM organization --   |t 5-stage pipeline ARM organization --   |t ARM instruction execution --   |t ARM implementation --   |t ARM coprocessor interface --   |g 5.  |t ARM Instruction Set --   |t Exceptions --   |t Conditional execution --   |t Branch and Branch with Link (B, BL) --   |t Branch, Branch with Link and eXchange (BX, BLX) --   |t Software Interrupt (SWI) --   |t Data processing instructions --   |t Multiply instructions --   |t Count leading zeros (CLZ - architecture v5T only) --   |t Single word and usigned byte data transfer instructions --   |t Half-word and signed byte data transfer instructions --   |t Multiple register transfer instructions --   |t Swap memory and register instructions (SWP) --   |t Status register to status register transfer instructions --   |t General register to status register transfer instructions --   |t Coprocessor instructions --   |t Coprocessor data operations --   |t Coprocessor data transfers --   |t Coprocessor register transfers --   |t Breakpoint instruction (BRK -architecture v5T only) --   |t Unused instruction space --   |t Memory faults --   |t ARM architecture variants --   |g 6.  |t Architectural Support for High-Level Languages --   |t Abstraction in software design --   |t Data types --   |t Floating-point data types --   |t ARM floating-point architecture --   |t Expressions --   |t Conditional statements --   |t Loops --   |t Functions and procedures --   |t Use of memory --   |t Run-time environment --   |g 7.  |t Thumb Instruction Set --   |t Thumb bit in the CPSR --   |t Thumb programmer's model --   |t Thumb branch instructions --   |t Thumb software interrupt instruction --   |t Thumb data processing instructions --   |t Thumb single register data transfer instructions --   |t Thumb multiple register data transfer instructions --   |t Thumb breakpoint instruction --   |t Thumb implementation --   |t Thumb applications --   |g 8.  |t Architectural Support for System Development --   |t ARM memory interface --   |t Advanced Microcontroller Bus Architecture (AMBA) --   |t ARM reference peripheral specification --   |t Hardware system prototyping tools --   |t ARMulator --   |t JTAG boundary scan test architecture --   |t ARM debug architecture --   |t Embedded Trace --   |t Signal processing support --   |g 9.  |t ARM Processor Cores --   |t Arm7tdmi --   |t Arm8 --   |t Arm9tdmi --   |t Arm10tdmi --   |t Discussion --   |g 10.  |t Memory Hierarchy --   |t Memory size and speed --   |t On-chip memory --   |t Caches --   |t Cache design - an example --   |t Memory management --   |g 11.  |t Architectural Support for Operating Systems --   |t ARM system control coprocessor --   |t CP15 protection unit registers --   |t ARM protection unit --   |t CP15 MMU registers --   |t ARM MMU architecture --   |t Synchronization --   |t Context switching --   |t Input/Output --   |g 12.  |t ARM CPU Cores --   |t ARM710T, ARM720T and ARM740T --   |t ARM810 --   |t StrongARM SA-110 --   |t ARM920T and ARM940T --   |t ARM946E-S and ARM966E-S --   |t ARM1020E --   |g 13.  |t Embedded ARM Applications --   |t VLSI Ruby Advanced Communication Processor --   |t VLSI ISDN Subscriber Processor --   |t OneC VWS22100 GSM chip --   |t Ericsson - VLSI Bluetooth Baseband Controller --   |t ARM7500 and ARM7500FE --   |t ARM7100 --   |t SA-1100 --   |g 14.  |t AMULET Asynchronous ARM Processors --   |t Self-timed design --   |t Amulet1 --   |t Amulet2 --   |t AMULET2e --   |t Amulet3 --   |t DRACO telecommunications controller --   |t self-timed future? 
650 7 |9 4776  |a Microprocesador. 
650 7 |9 1372  |a Procesamiento de datos. 
942 |2 ddc  |c LIBRO 
952 |0 0  |1 0  |2 ddc  |4 0  |6 004_165000000000000_F983_2000  |7 0  |8 AD  |9 10551  |a 1  |b 1  |d 2011-10-06  |l 3  |m 5  |o 004.165 F983 2000  |p 7949  |r 2022-11-16 00:00:00  |s 2022-11-16  |w 2011-10-06  |y AD  |k 3 
999 |c 6588  |d 6588 

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